module UART_Recieve(
	iRST_N,
	iRX,
	iCLK,
	iMode,
	oBUSY,
	oDATA,
	oADDR,
	oWE_N
);

input iRST_N,iRX, iCLK, iMode;
output  oWE_N;
assign oWE_N = ~iMode;
output reg[63:0] oDATA;
output reg[18:0] oADDR;
output oBUSY;
assign oBUSY = ~UART_IDLE;

reg [2:0] state;
reg prev_rdy;
reg [18:0] addr_cnt;
reg prev_Rdy;

always@(posedge iCLK or negedge iRST_N)begin	
	if(!iRST_N) begin
		addr_cnt <= 19'd0;
		state <= 3'b0;		
	end
	else begin		
		if(iMode) begin
			prev_Rdy <= UART_Rdy;
			if({prev_Rdy,UART_Rdy} == 2'b01) begin
				state <= 3'b0;
				oADDR <= addr_cnt;
				oDATA <= {56'd0, UART_Data};
				addr_cnt <= addr_cnt + 1'd1;
			end
		end
		else begin
			if(UART_EOP) state <= 3'd0;
			else begin
				prev_Rdy <= UART_Rdy;
				if({prev_Rdy,UART_Rdy} == 2'b01) begin
					case(state)
						0: oDATA[ 7: 0] <= UART_Data; 
						1: oDATA[15: 8] <= UART_Data; 
						2: oDATA[23:16] <= UART_Data; 
						3: oDATA[31:24] <= UART_Data; 
						4: oDATA[39:32] <= UART_Data; 
						5: oDATA[47:40] <= UART_Data; 
						6: oDATA[55:48] <= UART_Data; 
						7: oDATA[63:56] <= UART_Data; 					
					endcase
					state <= state + 1'b1;
				end
			end
		end		
	end
end

wire UART_Rdy, UART_WE, UART_EOP, UART_IDLE;
wire [7:0] UART_Data;

async_receiver u10(
	.clk(iCLK), 
	.RxD(iRX), 
	.RxD_data_ready(UART_Rdy), 
	.RxD_data(UART_Data),
	.RxD_endofpacket(UART_EOP), 
	.RxD_idle(UART_IDLE)
);

endmodule